FPGA compiler/simulator

The system uses AI techniques to automate the design and layout of ASIC's and GA's from undecorated specifications written in Java, C, C++ and FORTRAN.

The emphasis is on full automation. But you can get into the intermediate files (all in human-readable form) with a suit of tools or your trusty vi/emacs editor.

Run simulator on QRD problem

You get to type in how big the QR decomp is (can be non-square), and the compiler turns the C code into a netlist, lays it out on a fantasy FPGA, then simulates the FPGA. Only about 1 mn times slower than the real thing.

QRD source code

The compiler allocates some of this stuff to the netlist, and some to simulator hooks. A cmd line param specifies the X[][] are the sim outputs (also inputs :). The printf's are run in the simulator or host devel machine since FPGA's can't do them. Well... yet.

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